Memory devices, such as static random access memory (“SRAM”) and dynamic random access memory (“DRAM”), typically include arrays of memory cells for storing a digit of data in each of the memory cells. Depending on the charge, or voltage level, stored within a memory cell, the respective data digit may represent a logical low (e.g., a binary “0”) or a logical high (e.g., a binary “1”). For instance, a voltage level close to ground may represent a logical low or “0” and a voltage level close to a supply voltage for the memory device may represent a logical high or “1.”
Data digits stored in the memory cells are sensed through electrical paths. The electrical paths that carry the voltage representing a data digit so that the data may be sensed can be referred to as data lines, and are generally known in the industry as “digit” or “bit” lines, where those terms are used interchangeably. Digit lines may be precharged before the data stored in associated memory cells is sensed, because precharging the digit lines may allow faster sensing of the data stored in the memory cells. When a digit line, such as a bit line is precharged, the voltage level on the bit line is equalized to a voltage that is typically between the voltage levels corresponding to logical low and logical high. Accordingly, when the voltage level on a bit line begins to change to a new level due to charge sharing as a memory cell is accessed via the bit line, the range of voltage transition from the precharged level to the new level will typically be smaller than if the bit line was not precharged.
Sense amplifiers are typically used in memory devices for sensing and amplifying electrical signal representing data digits stored in memory cells. More specifically, bit lines are coupled to sense amplifiers so that electrical signals representing data bits stored in accessed memory cells (e.g., voltage levels or current flows) are coupled to sense amplifiers for sensing and amplification. A sense amplifier that senses a difference in current between the current flows on a complementary pair of bit lines coupled to the sense amplifier is generally known as a current sense amplifier. Likewise, a sense amplifier that senses a difference in voltage between the voltage levels on a complementary pair of bit lines coupled to the sense amplifier is generally known as a voltage sense amplifier. Whatever the case may be, in a sense amplifier the complementary pair of bit lines is precharged to the same voltage level prior to sensing and amplifying the electrical signal representing the data bit.
As the popularity of portable electronic devices continues to increase, demands for low-power, high-speed, and low-cost memory devices are consequently on the rise. With the low power requirement, the need for sense amplifiers to detect small voltage or current differential between the bit lines, which is often referred to as “bit line split”, becomes ever more important. One conventional approach is to employ short bit lines in the memory array architecture, thereby reducing parasitic capacitance in the bit lines in order to improve the minimum detectable bit line split. However, such approach carries with it the undesirable effect of larger overhead in terms of chip size. Moreover, as chip size continues to decrease, device variations such as mismatches in transistor characteristics and offsets in sense amplifiers generally makes it even more difficult to detect small bit line split in a low power setting.
Between current sense amplifiers and voltage sense amplifiers, current sense amplifiers generally provide better imbalance immunity, and therefore, tend to be able to detect smaller bit line split than voltage sense amplifiers. Current sense amplifiers also have higher sensing speed than voltage sense amplifiers in general. However, current sense amplifiers typically consume more power than voltage sense amplifiers do given that current sense amplifiers tend to waste some of the direct current during activation.
There is, therefore, a need for current sense amplifiers that can provide a balance in performance in terms of detection capability, sensing speed, and power consumption.